Carrier tapes are used to transport finished devices such as semiconductor dies. FIG. 1A illustrates a top view of a conventional carrier tape 100. The conventional carrier tape 100 has individual separate embossed pockets 110 to accommodate individual dies. The carrier tape 100 has fixed pitches 120 based on industry standards (e.g., 4 mm, 8 mm, 12 mm, etc.). When selecting a carrier tape for a product, it is best to minimize the pitch 120 to minimize the total length of the carrier tape 100 needed to ship the product.
The minimization of the pitch 120 is limited by a minimum space between the carrier tape pockets 110. This minimum space, referred to as a bridge, is labeled with element number 130 in FIG. 1A. Tape manufacturing processes require a minimum bridge 130 between the pockets 110 (typically >1.25 mm). As the pocket size is increased to accommodate larger devices, the space between the devices is decreased. If the pocket size for a given pitch is too large, then the only option is to increase the pitch 120 to the next higher increment, e.g., from 4 mm pitch to 8 mm pitch, as illustrated in FIG. 1B. For devices, increasing the pitch 120 increases the required amount of tape for a given quantity of the product, which in turn increases costs.
The conventional carrier tape 100 may include corner relief features 140 in the pockets 110 (see FIG. 1A), which are also referred to as “mouse ears”. Note that the mouse ears 140 are small. These small features are difficult, if not impossible, to tool and form. Moreover, the bridge 130—the gap between successive pockets 110—is reduced by the mouse ears 140. Thus, conventional corner relief measures such as the mouse ears 140 exacerbate the pitch issue described above.
Another issue of the conventional carrier tape 100 is as follows. As mentioned, the conventional carrier tape 100 has fully isolated, individual pockets 110. But as semiconductor devices become thinner and more fragile, it becomes a challenge to: (1) keep the thin devices from escaping the carrier tape pocket; and (2) prevent chip outs on the active surface of the device from impacts with the carrier tape pocket wall during vibration or drop shock events.
FIG. 2A illustrates a top view and FIG. 2B illustrates a cross sectional view of a conventional way to address issue (1). FIG. 2A illustrates the conventional carrier tape 100 of FIG. 1A rotated 90 degrees. So as to minimize clutter, not all element numberings from FIG. 1A are repeated. In FIG. 2A, it is assumed that a device 205 has been placed in each discrete pocket 110. Also, a clear cover tape 250 is placed over the top of the pocket 110 and runs parallel to the length of the conventional carrier tape 100 to seal the devices 205 within the pockets 110.
FIG. 2B is a cross-sectional view of the conventional carrier tape 100 taken along the dashed line of FIG. 2A. The width of the conventional carrier tape 100 is expanded in FIG. 2B so as to better illustrate the sealing provided by the conventional cover tape 250. As seen, the device 205 is placed within the embossed pocket 110. The conventional cover tape 250 is placed over the top of the pocket 110 and is heat sealed or adhered to the top surface of the conventional carrier tape 100. Note that the conventional cover tape 250 is above the top surface of the device 205.
Unfortunately, the conventional cover tape 250 can “puff up” to create a gap or a small open space 255 between the top surface of the conventional carrier tape 100 and the bottom surface of the conventional cover tape 250. This puff up condition is illustrated in FIG. 2C. Historically this gap 255 has not been an issue. However, as devices become thinner, the thin devices can fit in this space 255 and migrate out of the pocket. In other words, the conventional way of utilizing the conventional cover tape 250 does not fully address issue (1) of keeping the devices 205 within the pockets 110 of the conventional carrier tape 100.
The conventional way of utilizing the cover tape 250 also does not address issue (2). There is necessarily some X/Y gap between the edges of the device and the walls of the pocket 110. In FIG. 2D, it is illustrated that as the device 205 sits inside this embossed pocket 110, the device 205 is free to impact the pocket side walls during vibration and shock events such as drops. As fabrication technologies have advanced, the active surfaces of devices 205 have become more fragile, and the impacts with the pocket walls, e.g., during handling and transportation, can damage the devices 205. The devices 205 can be particularly sensitive to axial impacts on the conventional carrier tape reel because the impact shock is transmitted to the device 205 with minimal dissipation.
A further issue is the following. IC packages have historically followed very standardized outlines—typically square. This has made the task of standardizing package carriers possible. For example, as seen in FIGS. 1A and 1B, the spacings between the pockets 110 are regular. But recently, there has been a trend in customizing package sizes as well as a tremendous increase in wafer level packages (WLP). This has driven a huge increase in customized package carriers since the carrier pockets must be customized to fit the specific “non-standard” IC device package. Exacerbating this is the need to minimize any excess space between fragile WLP devices and the carrier pocket wall to minimize the potential for damage during transportation and handling. This situation has driven the need for customized tooling for package carriers. Unfortunately, this has also led to increases in development lead times and reduction in economies of scale, thereby keeping package carrier costs high.